What, Me Worry? : Is Your Design Team DFT-aware?

This post came about after reading John Ford's post about the value of a DFT education for designers. Forget appreciation, DFT is usually the least-understood specialization in the ASIC design flow.

In my opinion, DFT is not that easy to "get" primarily because it requires a viewpoint different from synthesis, timing and place-and-route. In those fields, you usually worry about timing, area and power. It's easier to apply your knowledge from synthesis to PNR. In DFT, you worry about fault coverage, controllability and observability; concepts alien to the rest of the ASIC design flow. It gets worse. More often than not, project and design managers are from a place-and-route, synthesis or timing background. Not many DFT engineers managing projects out there. Ergo: A clear understanding of DFT is lacking at most higher levels of the engineering hierarchy. Is it any wonder that DFT is the least of the design team's priorities?

What are your options? This list is AND'ed not OR'ed (do (1) AND (2) AND (3)...).

• Have a set of non-negotiable DFT rules that everyone has to follow. This would include ensuring controllability of resets and clocks, etc. I think it's important to have a list that is not open to negotiation (or else the DFT engineer ends up having to explain each and every rule to each and everyone). This is not a enlightened approach but it saves both DFT and non-DFT groups time and energy.
  
• Have a DFT checklist like John's that can be used by all designers to ensure DFT compliance. This list would be a checklist form of the aforementioned non-negotiable rules.
  
• Use a tool like Atrenta's Spyglass-DFT to check your RTL for DFT issues. Automated approaches to verify DFT compliance is so much more error-proof than looking through millions of lines of uncommented code.
• Have a very well-defined handoff mechanism between DFT and other functions to ensure minimum confusion for the non-DFT folks. The idea is to give them what they can use without knowing the first thing about DFT. Don' t explain the differences between scan shift, scan capture and scan transition modes to the STA engineers; give them a set of appropriate constraints (comes straight out of Tetramax, if you have it) that they can use as-is. Don't explain how to identify scan chains for re-ordering to the PNR engineers; give them a scandef file that can be read both in Synopsys and Magma.

Tags : Methodology, DFT, ASIC, VLSI

The DFT Arms Race: Technological Convergence of Test Solutions From Magma and Synopsys

Magma's Talus ATPG has put Magma very close (in technological terms) to matching Synopsys's test solutions. The first thing that struck me about the Talus press coverage was the high level of similarity between tool features touted by Magma and Synopsys.

#1 : Combinational On-Chip Compression. Synopsys projected Adaptive Scan's low-overhead fully-combinational architecture as revolutionary in comparison to sequential compression technologies from Mentor's TestKompress. Now, Magma claims their ATPG-X solution consists of a "stateless broadcaster" and a "combinational compactor" duo.

#2 : Slack-Aware Delay Testing. Propagating faults along the longest path in transition patterns rather than the easiest path was something Synopsys had been working on for some time now. The patent for this technology was filed in 1999 and granted in 2002! Yet, both Magma and Synopsys give press releases at the same time for this feature.

#3 : Concurrent Fault Detection. This one is just plain spooky. First, at SNUG 2007 Bangalore, we have a paper ( Concurrent Fault Detection : The New Paradigm in Compacted Patterns) on detecting multiple fault models using one pattern set using TetraMax. Now, it is claimed that "in Talus ATPG, when one fault model is targeted, other fault models are automatically simulated".

#4 : Just about Everything Else. Imitation , it is said, is the sincerest form of flattery. That said, imitation is also the first step in having the original eat your dust. From supporting industry standard STIL to diagnosis of compressed patterns, it appears that Magma has designed Talus ATPG to capitalize on Synopsys's success with TetraMax and DFT-Max.

The big difference, the one Magma is counting on, is the level of integration between test and place-and-route. It remains to be seen if this factor will be enough to overcome the dominance of DFT-Max and TetraMax.

Tags : DFT, Synopsys, Magma, EDA, Talus

The Last Bastion II : Some Q&A with DeFacto President and CTO Dr. Chouki Aktouf

In an earlier post, The Last Bastion Of DFT Tradition Falls : DeFacTo Technologies Introduces RTL Scan Insertion , I had listed some questions about HiDFT-Scan's capabilities. Dr. Chouki Aktouf (CTO, DeFacTo) was kind enough to answer these questions. Here's what Dr.Aktouf had to say about HiDFT-Scan.

Q : The change of methodology proposed is quite drastic. What's the easiest way adopt this flow in a phased manner?

The change in the overall test process is not that drastic; mainly you add DRC at RTL in conjunction with new checks (that now become possible) and displace gate-level scan insertion to RTL. HiDFT-Scan can be adopted progressively, IP-based for instance. The tool usage is also easy and accessible to RTL designers.

Q: Is HiDFT-Scan physically-aware when it comes to scan insertion?

Not physically aware, since we implement functional scan; but our scan is data-path sensitive. This ensures a good optimization during synthesis and P&R.

Q: Other EDA vendors are very much ahead in the DFT game and have very compelling DFT technologies. Synopsys has adaptive scan. Mentor has TestKompress. Is there a way to use HiDFT-Scan with tools from these vendors?

Absolutely. You can use HiDFT-Scan in conjunction with these tools. A typical example is TestKompress. Through HiDFT-Scan you can automatically access to TK and generate your final RTL including scan+test compression logic.

Q: Will we get a chance to see HiDFT in action?

If you are present at ITC, we will be pleased to talk to you at our booth #837.

Tags : DeFacTo, interview, HiDFT-Scan

The Last Bastion Of DFT Tradition Falls : DeFacTo Technologies Introduces RTL Scan Insertion

It had to happen. Someone would eventually come up with a way to insert scan onto RTL. Turns out that someone is DeFacTo Technologies of France. The tool is called HiDFT-Scan.

In some ways, this is a great idea:

• Scan insertion would be fast (as it works with RTL)
• Synthesis step between RTL ECOs and scan insertion is avoided
• Scan insertion is process/technology independent and can be ported easily to new nodes

But there are some questions that need to be answered:

• The change of methodology proposed is quite drastic. What's the easiest way adopt this flow in a phased manner?
• Is HiDFT-Scan physically-aware when it comes to scan insertion?
• Other EDA vendors are very much ahead in the DFT game and have very compelling DFT technologies. Synopsys has adaptive scan. Mentor has TestKompress. Will we have to abandon these vendors or will DeFacTo play well with others?

Tags : DFT, ASIC,scan insertion, EDA, DeFacTo