Everything's Connected : An Opportunistic View On Butterfly Effects In Physical Design

The emergence of physical synthesis technologies (such as DC-Topographical from Synopsys and First Encounter SVP from Cadence) is usually attributed to the following:

• Increasing interconnect delay:gate delay ratio
• Imprecise prediction of wire delays using wire load models

While the above is certainly true, it does not seem to be the whole story. It seems to me that the whole problem is that there are additional cost functions that cannot possibly be accounted for without placement and global routing. When it comes to logical synthesis (without physical information), tools have no choice but to optimize paths independently. If there is no combinational connection between two paths, synthesis is not in a position to perform any possible trade-offs between these two paths. A cost function combining timing, area and power is applied to each path independently.

When it comes to physical design, two additional cost functions come into play:

• Placement : How can the cells in the design be placed to optimize area, timing and power?
  
• Routing: Can this placed design be routed?

Placement and routing put a new spin on things because hitherto un-related paths (as seen by logic synthesis) start to affect each other through these functions. The logical synthesis cost function has zeros where placement and routing ought to be. In other words, synthesis assumes that each cell in the design will be placed perfectly. The reality, of course, is far removed from this utopian vision. The best metaphor I can think of for this phenomenon is crosstalk. Can your synthesis tool synthesize for crosstalk avoidance? No.There is no correlation between logical connectivity and aggressor-victim relationships. You have to find the aggressors and victims after detailed routing.

But the problem can also be viewed as an opportunity. Since physical design causes un-related paths to interact, one can play around with non-critical paths to close the design without directly optimizing your critical paths. Like everything else, it pays to see the big picture.


Tags : ASIC, VLSI

Force Multipliers : A Paradigm for Technology and Tool Development

The concept of force multipliers originated in military science. Force multipliers are fulcrums that allow you to have an effect that is exponentially proportional to the amount of resources employed. Radar is a good example of a force multiplier. An air force that uses radar will be able to successfully attack or fend off a much larger force that does not have the benefit of the technology simply by being able to track their opponents in the battlefield. Sometimes, the force multiplier does not physically exist. For example, the coordinated use of air and ground forces as a blitzkrieg is more effective than an uncoordinated force of the same size. The blitzkrieg tactic is the force multiplier in this case.

It seems to me that viewing tools and technologies as force multipliers is a good paradigm for guiding technology and tool development.

1. Force multipliers do not replace; they complement. Did they disband the air force after inventing radar? The objective of tool development in a force multiplier context should not be to create a software version of your engineer. It's about creating a tool that will allow them to control a lot with very little. In a design environment such as Pyramid or IC-Catalyst, the engineer is in control but the environment takes care of all the small stuff (generating scripts, checking reports, firing jobs...). An engineer using a design environment is in a position to accomplish a lot with very little effort.
2. Force multipliers need not be complex; just effective. Creating and supporting a complete design environment is a lot of work. plus, there's always the chance that you're over-solving the problem. Small utilities addressing the right issues in the flow can add value with much less effort. Think scalpels, not broadswords.
3. Force multipliers need not physically exist.A stable design methodology does not physically exist, and yet, guides the engineer in the direction that will produce the optimal result in the shortest time.
4. Force multipliers stack. The effect of more than one force multipliers is not the sum of their individual effects but their product. For example, a good hierarchical methodology and a good timing fix utility employed together will accelerate timing closure beyond the sum of their individual effects.

Tags : ASIC, VLSI