Distributed EDA Meets Accelerated Hardware: Gauda's OPC Points The Way

In Divide And Conquer, I made some arguments for the inevitable dominance of distributed algorithms in the EDA industry. In Need For Speed, I argued for, among other things, using graphics card-based acceleration for EDA (Nvidia's CUDA technology).

What happens when these two get together? Gauda's new optical proximity correction (OPC) tool. The tool not only uses existing graphic cards (from the likes of Nvidia and the erstwhile ATI) but also uses sophisticated distributed algorithms to accelerate OPC upto 200x (really? 200x??) faster. Rather than a flash in the pan, I'd say Gauda is the pioneer in a direction that is soon to be well-traveled by the EDA biggies.

Tags : EDA, Distributed Computing, ASIC, VLSI

Will The Real ASIC Please Stand Up? : The Brave New World Of Counterfeit ASICs

Just last week, Reuters reported that counterfeit components worth $1.3 Billion were seized in a joint operation by the US and the EU. Chew on these stats:

• These counterfeits must be pretty sophisticated. Biggies like Intel, Phillips and Cisco are not exactly known for making great op-amps.
  
• Counterfeiters are going after the big-ticket items. If 360,000 parts were seized, that puts the average value of the components seized at $3600!

Counterfeit ASICs bring us face to face with an altered reality. You can fake a watch, a perfume or even clothing, but an ASIC? Counterfeits used to be something Nike and Armani worry about, not ASIC design companies. Clearly, we're not in Kansas anymore. The big questions are:

• Do these counterfeits actually work??
• How are ASICs reverse-engineered?
  
• Do they use the datasheet/spec?
  
• Do they obtain the GDSII?
• Do they strip the die layer by layer?
  
• Can we prevent an ASIC from being faked?
  
• If the datasheet and the chip are out in the real world, can we prevent a copy?
  
• Can we authenticate an ASIC beyond doubt?
• What prevents them from copying that, too?

Tags : Counterfeit, ASIC, VLSI

The EDA Universe : Now in PDF!

EDA DesignLine has published the PDF format of Gary Smith's EDA charts! You can read IC Design Tools Vendors Reference Chart (@ EDA Designline) to get the back story on this. The PDFs can be downloaded from the following links:

• RTL and Gate Level EDA Companies
  

• IC-CAD and PCB Companies
  

• SDA (System Design Automation) and ESL Companies

Tags : EDA, ASIC, VLSI

I Coulda Been A Contender : Some VLSI Ideas I Wish I Had Had (First)

Getting out plan for the new year got me thinking about issues in the ASIC flow and what could (or should) be developed to make the flow better. It could be a new technology, a new tool or a new flow even. The hardest part of this is to be able to break out of the box and approach issues from a new angle. Naturally, at such times, I look back at some ideas I heard about and think "I wish I'd thought of that!" It's not that these ideas made their inventors rich but they did make me sit up and take notice because of their refreshingly different viewpoint. Here's hoping they make you think, too.

• Wire Tapering : Minimize the delay of a wire by controlling its shape. Rather than the usual rectangular shape, the optimal shape (in terms of delay) for an interconnect is exponentially tapered. The wire will be thickest near the driver and thinnest near the sink. In a regular net, the capacitance of the end section of the wire is the same as the initial section of the wire. Since the end capacitance has to be driven through a large resistance (basically the resistance of the whole net), the driver "sees" this end capacitance as a large load. By tapering the interconnect, the capacitative load decreases with distance from the driver. Thus, the overall load seen by the driver for a tapered net is lesser than a rectangular one.
  

• Configurable Processors : Adapt a processor's instructions to match the application. Most processors are jacks of all trades but masters of none. Though processor cores are not particularly good at anything, using them for implementing features has its advantages. There's low risk of functional bugs within the core itself. Fixing bugs and adding features is as easy as updating the firmware. This is the low-performance/low-effort solution. Custom RTL, on the other hand, is the high-performance/high-effort solution. Implemented features have high performance but verification requires a lot of effort and bug fixes and additional features will atleast require a respin. Configurable processors allow you to get the best of both worlds. By implementing an instruction set tailored to the end application, the performance of the core is increased while verification and feature updates and bug fixes are still relatively easy.
  

• Channel-less Floorplan: Why not just route top-level signals through the block? Look at the channels in your hierarchical floorplan (the gaps between the blocks). You need these channels to be able to route top-level signals from block to block. Usually, these signals don't undergo logical transformations at the top-level so it's pretty much getting the signal from point A to point B using repeaters. In a channel-less floorplan, the repeaters don't go round or over the block; They go through the block. The idea is to create feedthroughs in blocks such that a signal can use these feedthroughs to get to the other side of the block faster. The benefit is that you save on the die area that was previously dedicated to channels.

• Asynchronous ASIC Design: What if there were no clocks? Clocks are nothing but synchronization signals. At each clock edge, you are guaranteed that the input data is stable and valid. The problem with having a clock is that your design can run only as fast as the worst path in the design. Even if 99.99999% of paths run at 1ns , the last path running at 2ns requires you to run the entire design at 500MHz. Wouldn't it be great if the performance of the entire device did not depend on the worst path in the design? That's where asynchronous designs come in. Asynchronous ASIC designs do not require a clock. Instead of clock-based synchronization, these designs use handshaking, semaphores and other methods to exchange data. Each part of the device runs as fast as it can and the effective frequency of operation is no longer determined by the worst path in the design. Other benefits of asynchronous design include lesser power dissipation (no clock trees) and lesser dynamic IR drop issues (without clocks, transitions in the design are randomized).

• Analog Computing: Forget binary and use (semiconductor) physics. There's something unnatural about digital design. In a world where everything sentient is analog, should computing be any different? The idea behind analog computing is to use physical laws for computation. Suppose you want to build an adder, currents equivalent to the numbers to be added are passed through a resistance. The voltage drop across the resistance is proportional to the sum. The square-law characteristic of the MOS transistor in saturation is used to create computation devices such as multipliers. By piggy-backing onto the mathematics of physical effects, it is possible to use analog for computation at a fraction of the delay, area and power of digital circuits.

Tags : ASIC, VLSI