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    Thursday, June 19, 2008

    (Even More) Useful Skew : Teklatech Adapts Useful Skew Concepts To Close Dynamic IR

    Zero clock skew is not a necessary thing. As long as timing can be closed, clock skew is immaterial. This kind of thinking is what gave birth to the concept of useful skew. The use of useful skew in contemporary design is mostly restricted to timing closure. In this method, the arrival of clock edges at the launch and sink registers of critical paths are changed to increase the effective clock period available to the critical path. Since different registers have different clock latencies, one side-effect of this optimization is that all your registers don't transition at once.

    But is there a benefit from having all your registers transition at different times? Enter Dynamic IR (stage left). When a large number of transitions occur in a very short period of time (right after the active clock edge, for example), the power network is not in a position to supply such a large amount of current in such a short space of time. Result: large and localized instantaneous drops.

    Teklatech's FloorDirector uses useful skew concepts to spread out the register transitions by playing around with the clock edges and thus reduces the dynamic IR drop problem without affecting timing. Elegant, huh?

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    Out Now! : TSMC Reference Flow 9.0 Is Now Available

    The TSMC Reference Flow 9.0 is available for download from TSMC-Online. Eyecatching items include:

    • DFT
      • Using E-fuse for MBIST
      • Failure Analysis
      • Low-power ATPG
    • Really Advanced CTS
      • CTS for Dynamic IR
      • CTS for Low-power
      • Multi-Mode Multi-corner CTS
    • Low-power
      • Low power automation with UPF
    • Statistical Design
      • {LPC, CAA, VCMP} --> {Timing, Power, Leakage} Flows

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    EDA BlogRoll : All The Blogs In One Place

    The EDA Blogroll is an excellent resource to keep yourself up-to-date on the EDA/VLSI blogosphere. Not just links ! comes with a built-in RSS reader,too. Check it out.

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    Thursday, June 12, 2008

    SNUG 2008 : Registrations Open

    In case you're a Synopsys customer in Bangalore, registration for SNUG2008 is now open. Why, Aditya, thank you for that perfectly selfless propagation of useful information with no ulterior motives....


    If you can, do try and attend my presentation (in the Synthesis & Test track) on the 10th of July.

    Register Cloning For Accelerated Design Closure

    Multiple technologies exist to achieve timing closure on critical paths. One such technology, clock skew optimization, changes the arrival of clock edges at the launch and sink registers to increase the effective clock period of the critical path. Standard clock skew optimization does not necessarily utilize the full slack available at the input of a register but only the amount required to resolve the setup violations on paths from the register. If clock skew optimization were to utilize the input slack to the fullest extent towards have a large setup slack on the erstwhile critical path, it could accelerate setup timing closure by letting the tool concentrate on other paths in the design. However, the process could also introduce a large number of hold violations on other paths from the register with low hold slack due to the early launch of data. By having separate clone registers for setup and hold paths, one can fully utilize the input slack to launch registers for accelerating timing closure while limiting resultant hold violations. Since cloned registers are exact copies of the original register, the impact of register cloning on verification and ECO methodology effort is minimized. In this paper, a methodology will be presented to identify cloning candidates, insert clone registers and verify the final design against the un-cloned input.

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    Wednesday, June 11, 2008

    Everything's Connected : An Opportunistic View On Butterfly Effects In Physical Design

    The emergence of physical synthesis technologies (such as DC-Topographical from Synopsys and First Encounter SVP from Cadence) is usually attributed to the following:

    • Increasing interconnect delay:gate delay ratio
    • Imprecise prediction of wire delays using wire load models
    While the above is certainly true, it does not seem to be the whole story. It seems to me that the whole problem is that there are additional cost functions that cannot possibly be accounted for without placement and global routing. When it comes to logical synthesis (without physical information), tools have no choice but to optimize paths independently. If there is no combinational connection between two paths, synthesis is not in a position to perform any possible trade-offs between these two paths. A cost function combining timing, area and power is applied to each path independently.

    When it comes to physical design, two additional cost functions come into play:
    • Placement : How can the cells in the design be placed to optimize area, timing and power?
    • Routing: Can this placed design be routed?
    Placement and routing put a new spin on things because hitherto un-related paths (as seen by logic synthesis) start to affect each other through these functions. The logical synthesis cost function has zeros where placement and routing ought to be. In other words, synthesis assumes that each cell in the design will be placed perfectly. The reality, of course, is far removed from this utopian vision. The best metaphor I can think of for this phenomenon is crosstalk. Can your synthesis tool synthesize for crosstalk avoidance? No.There is no correlation between logical connectivity and aggressor-victim relationships. You have to find the aggressors and victims after detailed routing.

    But the problem can also be viewed as an opportunity. Since physical design causes un-related paths to interact, one can play around with non-critical paths to close the design without directly optimizing your critical paths. Like everything else, it pays to see the big picture.

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