The emergence of physical synthesis technologies (such as DC-Topographical from Synopsys and First Encounter SVP from Cadence) is usually attributed to the following:
- Increasing interconnect delay:gate delay ratio
- Imprecise prediction of wire delays using wire load models
While the above is certainly true, it does not seem to be the whole story. It seems to me that the whole problem is that there are additional cost functions that cannot possibly be accounted for without placement and global routing. When it comes to logical synthesis (without physical information), tools have no choice but to optimize paths independently. If there is no combinational connection between two paths, synthesis is not in a position to perform any possible trade-offs between these two paths. A cost function combining timing, area and power is applied to each path independently.
When it comes to physical design, two additional cost functions come into play:
- Placement : How can the cells in the design be placed to optimize area, timing and power?
- Routing: Can this placed design be routed?
Placement and routing put a new spin on things because hitherto un-related paths (as seen by logic synthesis) start to affect each other through these functions. The logical synthesis cost function has zeros where placement and routing ought to be. In other words, synthesis
assumes that each cell in the design will be placed perfectly. The reality, of course, is far removed from this utopian vision. The best metaphor I can think of for this phenomenon is crosstalk. Can your synthesis tool synthesize for crosstalk avoidance? No.There is no correlation between logical connectivity and aggressor-victim relationships. You have to find the aggressors and victims after detailed routing.
But the problem can also be viewed as an opportunity. Since physical design causes un-related paths to interact, one can play around with non-critical paths to close the design without directly optimizing your critical paths. Like everything else, it pays to see the big picture.
Tags : ASIC, VLSI
Technologies like DCT seem very appealing. I always wonder about the repeatability of physical estimation done in synthesis vs. what will ultimately happen in P&R. What if the floorplan is different? What if the vendors are different for synthesis vs. P&R? Does it still correlate? Is it at least better than wireload model synthesis?
ReplyDeleteJohn
http://jab-semi.blogspot.com/
That's true about repeatablity. When your place-and-route tool and synthesis tool don't speak the same language, it could be an issue. Usually, even with minimal information, the critical paths and slacks correlate very well across vendors. It's the other 99.99% that vary to some extent based on the difference in algorithms. It's always better to give the synthesis tool as much information as possible (floorplan, pin locations, routing blockages, placement blockages...) for increased correlation. Physically-aware synthesis, in my opinion, is not a one-shot solution . Since the placement engine embedded in the synthesis is a reduced version of the real thing, the actual post-placed metrics will vary from synthesis results (but to a lesser degree than synthesis with wireloads). I see physically-aware synthesis adding value by enabling the right architectural choices for RTL constructs that can be further fine-tuned using the pnr tool.
ReplyDeletephysically-aware synthesis, from what I have seen, beats {zero, custom, standard} wireload models when it comes to correlation. physically-aware synthesis may not be perfect but it is a good distance ahead of the wire-load methods.