I remember reading somewhere that the state-of-the-art EDA tools always lag the state-of-the-art design practices in the ASIC industry. Before an EDA tool or a feature is created to solve a problem, an engineer in an ASIC design company had already figured out how to use existing EDA tools to accomplish the same thing. The solution in the engineer's case could be a simple workaround or, sometimes, a complete tool/script using the EDA tool's command language. The key element of success in such endeavors is the EDA tool's support for user access to low-level functions and data structures. The argument here is that, when EDA tools support user access to low-level data structures and functions, it is a win-win situation.
- Unintended Uses: EDA tools are like goldmines. For example, a static timing analysis tools contains within it robust high-speed parsers (verilog, SDF, SPEF...) and network analysis functions. When the EDA tool architect allows access to these functions (and the resultant data structures), he or she opens the door to a wide range of uses for the tool. The design engineer does not have to write his or her own functions and can leverage the functions from EDA tools (win). Increased usage of the EDA tool implies increased license requirement which leads to increased revenue for the EDA company (win).
- Advancing the State Of The Art : The only thing constant in the industry is workarounds. No matter how sophisticated the tool, someone somewhere wants something that the tool doesn't support yet. This is a good thing. Before there was a synthesis tool that supported clock-gating, designers with clock-gated designs would adapt an existing synthesis tool to support clock-gating through workarounds and scripts. Eventually, a future generation of the synthesis tool would have native support for clock-gating utilizing, in no small measure, the learnings from these tools and scripts. The designer engineer is free to utilize existing tools for advancing design methodologies (win) while EDA companies learn from these trailblazers to improve their tools (win).
- Maintain the Status Quo : Switching EDA vendors is particularly painful. Along with the switch, a lot of tool-related know-how (scripts, methodologies, workarounds, known issues...) is invalidated. The design engineer is forced the relearn and redo everything. Obviously, this switch is just as painful to the EDA vendor as it constitutes a loss of current and future revenue from the concerned ASIC design company. Apart from performance, one of the usual suspects that force the switch is gaps in the EDA tool's capabilities. When the tool cannot be tweaked, cajoled or coerced to meet the designer's requirements, the engineer has no choice but to go shopping. By providing deep access, the EDA tool can be used to meet the designer's requirement. The design engineer does not lose time ramping up on a different tool (win) and the EDA company does not take a revenue hit (win).
