In The Shameless Pursuit Of Average : Uniformity As A Metric In Physical Design

Physical design tools aim to create a placed and routed design exhibiting the best area, timing and power. As one progresses to smaller technology nodes, the additional steps in the flow deal with more localized phenomena.

• Dynamic IR drop is a local phenomenon in both time and space. It occurs when a group of cells in the same region switch at the same time.
  
• DFM-related phenomena such as CMP effects and CAA hotspots are local in space. They occur due to the layout geometries in a very small window area.

The usual approach in the ASIC design flow is to implement the design first and fix violations due to local effects later. This is a valid trade-off. The overhead in tracking or resolving local effects while implementing the whole design would be high so it makes sense to follow the "design-first-fix-later" approach. Is there another effective way to skin this cat? Let's state our problem in this way:

Local violations occur when local phenomena are far from the full-chip average.

• If the power consumption in a small window is larger than the design average, there would be more static IR drop in that window.
  
• If the power consumption is high in both a small layout window as well as a small timing window, it would result in dynamic IR drop violations.
• If the routing density in a local window is high, it would result in CAA hotspots
• If the routing density in a local window is too low, it would result in CMP hotspots

The obvious solution that presents itself is:

Rather than fix violations later, add uniformity as a cost function in physical design tools to avoid the occurrence of violations in the first place.

• If uniform power density is added to the tool's cost function, we would not see large static IR drop in local layout windows.
• If we can spread power density in both time and space, dynamic IR violations can be reduced as no local layout window will consume a large amount of power in a small time window.
• If we can add uniform routing density as part of the cost function, we can avoid CAA hotspots a priori rather than spreading out wires later.

Tags : ASIC, VLSI