Much has been said about the shift from corner-based sign-off to statistical sign-off. Most of the material has been focusing on the use of statistical timing analysis and statistical extraction to alleviate the pessimism and effort associated with corner-based sign-off. What no one has been touting is a complete statistical solution. Design in the statistical domain is a paradigm shift and cannot but help affect the entire RTL2GDSII flow. In the absence of a complete solution, there's a "lost in translation" scenario when a design transitions from corner-based implementation into statistical sign-off. Put bluntly, is there sense in adopting statistical sign-off while the rest of the flow supports only corner-based analysis?
The smart money says that statistical design is here to stay. In that case, the complete solution is already on its way. But, right now, we are in a no-man's land between corner-based design and statistical design. What are our choices?
- Short-term Gain/ Long-term Pain. Use corner-based flows until a complete statistical solution is in place. Nothing needs to change as of now. Of course, the transition will be widespread and painful when it is attempted.
- Short-term Pain/ Long-term Gain. Adapt non-statistical implementations tools to work with existing stat-aware tools. The transition into a complete solution will be gradual. The pain here is that of adapting non-statistical tools to fit into a statistical design flow. Lots of workarounds, custom scripts that will eventually be rendered obsolete by the arrival of eda tools with native stat support.
Tags : ASIC, VLSI
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