The Hidden Factory : First Time Yield In The ASIC Design Flow

The Six Sigma methodology is widely used to redesign processes to be more efficient. The way Six Sigma works is to redesign a process to all but eliminate defective outputs. To achieve Six Sigma, a process must create no more than 3.4 defects per million opportunities. Why the focus on defects?

• Defects = Waste: When a process creates a defective output, all the effort and material invested in that defective part is essentially wasted.
• Defects = Rework: When an intermediate stage produces a defective output, the process for that stage is repeated to produce a correct output.

Focusing on eliminating defects in a systematic manner allows a process to be both more efficient as well as produce outputs of consistently high quality.

One of the key measures of process quality used in Six Sigma is First Time Yield(FTY). The first time yield of a single stage is the probability that a correct output is created if the stage is run exactly once. The first time yield of a process is the product of the first time yield of its stages.

FTY is great for identifying priority areas for redesign. Think of a simple process consisting of two stages: A and B. The FTY of A is 50%. The FTY of B is 100%. The FTY of the entire process is 50% (100% * 50% ). Stage B is perfect but Stage A is bringing down the FTY of the process. Another benefit of FTY is to identify "hidden factories". What if stage A is followed by a quality check stage that mandates a rerun of A in case of defective outputs? If we were to insert a QC check stage between A and B, the process as a whole will have 100% yield. But, stage A will be repeated twice on average to produce a correct output for a given input. When you view the process as a black box, you would not see these stage A iterations. For this reason, these iterative loops are called hidden factories. So, a process of multiple stages can produce a million correct outputs for a million correct inputs and still not be a good process.

Consider your ASIC Design Flow in this context:

• What are the chances that a design will go through your ASIC Design Flow in one shot?
• What are the chances of a particular flow (synthesis, scan insertion,...) will go through in one shot?
  
• Which flow is bringing you down?
• Where are the hidden factories?
• What are you going to do about it?

Tags : ASIC, VLSI