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    Thursday, December 20, 2007

    Death, Taxes and ECOs : The Inevitability Of Functional Errors Is An Opportunity

    There was a great article in EETimes a couple of weeks back titled Virtually Every ASIC ends up as an FPGA that I'd summarize thus:

    • Functional verification is becoming more of a problem with increasing number of transistors being crammed onto a die
    • Simulation is slowly becoming a non-viable option for functional verification (both in terms of time and test vector generation)
    • Prototype FPGAs of your design allow your to apply millions of vectors per second (since you can run the FPGA at high speed) and debug issues much faster.
    • FPGA is the new testbench.
    Here's a thought:
    • How can a RTL-to-GDSII flow add and extract value in a world where FPGAs are used for functional verification?
    • Is that really necessary? Yes. According to the article, 60% of ASIC respins are to fix logical/functional errors and 90% of all ASICs are prototyped as FPGAs
    If you could tune your flow to exploit this reality, you have an advantage executing (or bidding for) 60-90% of all ASIC designs!

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    1. I doubt that 90% of ASICs are prototyped with FPGA. I think it's often too much trouble to set up both ASIC and FPGA implementation and verification flows.

      Maybe this is part of the author's point, that it needs to be easier to prototype ASICs with FPGA. And I'm sure that Synplicity has tools they'd be happy to have help you do that. :-)

      John's Semi-Blog

    2. It would be interesting to know what you think are worth-solving research problems in ECO domain...

      I am doing some work on ECO, so I am curious to know what practical problems do ppl encounter with existing tools and if at all, any academic research is required in any particular direction..