Death, Taxes and ECOs : The Inevitability Of Functional Errors Is An Opportunity

There was a great article in EETimes a couple of weeks back titled Virtually Every ASIC ends up as an FPGA that I'd summarize thus:

• Functional verification is becoming more of a problem with increasing number of transistors being crammed onto a die
• Simulation is slowly becoming a non-viable option for functional verification (both in terms of time and test vector generation)
• Prototype FPGAs of your design allow your to apply millions of vectors per second (since you can run the FPGA at high speed) and debug issues much faster.
• FPGA is the new testbench.
  

Here's a thought:

• How can a RTL-to-GDSII flow add and extract value in a world where FPGAs are used for functional verification?
• Is that really necessary? Yes. According to the article, 60% of ASIC respins are to fix logical/functional errors and 90% of all ASICs are prototyped as FPGAs

If you could tune your flow to exploit this reality, you have an advantage executing (or bidding for) 60-90% of all ASIC designs!

Tags : Methodology, ASIC, VLSI