Will It Blend? : Combining ASIC, FPGA and Structured ASIC On A Single SoC

The availability of structured ASIC IP for use within standard SoC creates yet another option for ASIC design houses seeking to balance NRE, per-unit cost and time-to-market. You can see the announcement by ChipX here. If this trend keeps up, the options available to ASIC design houses when it comes to design implementation will be a blend of implementation technologies where designers choose the optimal mix of FPGA, structured ASIC and standard cell technologies to hit their target NRE-UC-TTM sweet spot. There was at least one company, Leopard Logic, that created FPGA IP that could be embedded into a standard SoC. Just a short hop to a company offering all three technologies on the same die.

Think of the advantages that each approach bring to the table:

• FPGA : Highly configurable, Fast Time-to-Market , Low performance
  
• Standard Cells : Zero configurability, High time-to-market, High performance
• Structured ASIC : Medium configurability, Medium time-to-market, Medium performance

Can we have the advantages of all the three if a SoC is built using all three technologies? Just flip the equation.

• Blocks that require configurability but can live with low performance : use FPGA IP
  
• Blocks that require high performance : use Standard cells
  
• Blocks that require medium configurability but only medium performance : use structured ASIC IP

Are we heading towards the universal ASIC design flow that can handle all three technologies on a single die?


Tags : Methodology, FPGA,ASIC, VLSI